Defect and Error Tolerance in the Presence of Massive Numbers of Defects

Authors:
M. A. Breuer;S. K. Gupta;T. M. Mak
Affiliations:
Univ. of Southern California, Los Angeles, CA, USA;-;-
Venue:
IEEE Design & Test
Year:
2004

Citing 1
Cited 29

An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes

ITC '02 Proceedings of the 2002 IEEE International Test Conference

Let's Think Analog

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Going beyond TMR for protection against multiple faults

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dependable ≠ unaffordable

Proceedings of the 1st workshop on Architectural and system support for improving software dependability
Estimating Error Rate in Defective Logic Using Signature Analysis

IEEE Transactions on Computers
A framework for system reliability analysis considering both system error tolerance and component test quality

Proceedings of the conference on Design, automation and test in Europe
Reduction of detected acceptable faults for yield improvement via error-tolerance

Proceedings of the conference on Design, automation and test in Europe
Functionally Fault-tolerant DSP Microprocessor using Sigma---delta Modulated Signals

Journal of Electronic Testing: Theory and Applications
Multi-vector tests: a path to perfect error-rate testing

Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Instruction-Level Fault Tolerance Configurability

Journal of Signal Processing Systems
Reliability analysis of logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Yield analysis of partial defect tolerant bit-plane array

Computers & Mathematics with Applications
Green: a framework for supporting energy-conscious programming using controlled approximation

PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Computation as estimation: a general framework for robustness and energy efficiency in SoCs

IEEE Transactions on Signal Processing
Approximate logic synthesis for error tolerant applications

Proceedings of the Conference on Design, Automation and Test in Europe
Gate-level redundancy: a new design-for reliability paradigm for nanotechnologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power multimedia system design by aggressive voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fault-tolerant interconnect mechanism for NMR nanoarchitectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power JPEG2000 encoder with iterative and fault tolerant error concealment

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sampling + DMR: practical and low-overhead permanent fault detection

Proceedings of the 38th annual international symposium on Computer architecture
Error Rate Estimation for Defective Circuits via Ones Counting

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Perceptual quality preserving SRAM architecture for color motion pictures

Proceedings of the Conference on Design, Automation and Test in Europe
A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects

Journal of Electronic Testing: Theory and Applications
Methods for fault tolerance in networks-on-chip

ACM Computing Surveys (CSUR)
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Neural Network Guided Spatial Fault Resilience in Array Processors

Journal of Electronic Testing: Theory and Applications
Design of the coarse-grained reconfigurable architecture DART with on-line error detection

Microprocessors & Microsystems

Quantified Score

Hi-index	0.01

Visualization

Abstract

As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. This article introduces a new approach for error tolerance resulting in chips containing only errors acceptable for such applications.