Defect-Oriented Testing and Defective-Part-Level Prediction
IEEE Design & Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
On Efficiently and Reliably Achieving Low Defective Part Levels
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
All Tests for a Fault Are Not Equally Valuable for Defect Detection
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Enhanced testing performance via unbiased test sets
EDTC '95 Proceedings of the 1995 European conference on Design and Test
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On the decline of testing efficiency as fault coverage approaches 100%
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
On the Use of Fault Dominance in n-Detection Test Generation
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
Intelligible Test Techniques to Support Error-Tolerance
ATS '04 Proceedings of the 13th Asian Test Symposium
Computing Architectural Vulnerability Factors for Address-Based Structures
Proceedings of the 32nd annual international symposium on Computer Architecture
Analysis and Testing for Error Tolerant Motion Estimation
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
ATS '06 Proceedings of the 15th Asian Test Symposium
Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
Identification of Critical Errors in Imaging Applications
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis
ATS '07 Proceedings of the 16th Asian Test Symposium
Multi-vector tests: a path to perfect error-rate testing
Proceedings of the conference on Design, automation and test in Europe
Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Threshold testing: improving yield for nanoscale VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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When testing resources are severely limited, special attention should be paid to critical faults/defects so that important or frequent field failures arising from test escapes can be minimized. We present a new algorithm to optimize test sets aimed at significantly reducing the criticality of test escapes--especially for very short test sets that may be applied in the field. The algorithm proposes an exponential-based test set quality model to evaluate the criticality of potential undetected defects and develops a programming model to search for a test set that effectively reduces this criticality.