Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
Reduction of detected acceptable faults for yield improvement via error-tolerance
Proceedings of the conference on Design, automation and test in Europe
Testable design techniques for variable block size motion estimator used in H.264/AVC
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Multi-vector tests: a path to perfect error-rate testing
Proceedings of the conference on Design, automation and test in Europe
Instruction-Level Fault Tolerance Configurability
Journal of Signal Processing Systems
Threshold testing: improving yield for nanoscale VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software adaptation in quality sensitive applications to deal with hardware variability
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Hardware that produces bounded rather than exact results
Proceedings of the 47th Design Automation Conference
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testable design techniques for variable block size motion estimator used in H.264/AVC
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
Neural Network Guided Spatial Fault Resilience in Array Processors
Journal of Electronic Testing: Theory and Applications
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We propose a novel system-level error tolerance approach specifically targeted for multimedia compression algorithms. In particular we focus on the motion estimation process performed by most video encoders. While current manufacturing process classifies fabricated systems into two classes, namely, perfect and imperfect, our proposed scheme employs categories which are based on acceptable/unacceptable performance degradation. By enabling the use of systems that would otherwise have been discarded we seek to increase the overall yield rate in the system fabrication process. To achieve this, we propose testing algorithms that aim at determining if faults in a given chip produce acceptable performance degradation, and we propose a technique which can cancel the effect of those among the acceptable faults that can be compensated.