Testable design techniques for variable block size motion estimator used in H.264/AVC

Authors:
Po-Yu Yeh;Bo-Yuan Yeh;In-Yi Cheng;Sy-Yen Kuo;Shyue-Kung Lu
Affiliations:
Dep. of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Dep. of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Dep. of Information Management, National Taipei University of Science and Technology;Dep. of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Dep. of Electronic Engineering, Fu Jen Catholic University, Taipei, Taiwan
Venue:
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Year:
2006

Citing 6
Cited 0

Easily Testable Iterative Logic Arrays

IEEE Transactions on Computers
Analysis and Testing for Error Tolerant Motion Estimation

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
The Complexity of Fault Detection Problems for Combinational Logic Circuits

IEEE Transactions on Computers
An efficient VLSI architecture for H.264 variable block size motion estimation

IEEE Transactions on Consumer Electronics
An efficient hardware implementation for motion estimation of AVC standard

IEEE Transactions on Consumer Electronics
A novel all-binary motion estimation (ABME) with optimized hardware architectures

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, testable design techniques for variable block size motion estimators used in H. 264/AVC are proposed. The whole motion estimator can be viewed as an iterative logic array (ILA) consisting of basic cells (modules). Design-for-testability techniques are applied for the cell (module) function such that the M-testability conditions proposed in previous works can be met for the motion estimation array. The goal of the DFT techniques is to make the cell (module) function bijective. The M-testability conditions guarantee 100% single-cell (module)-fault testability with a minimum number of test patterns. The hardware overhead and the number of test patterns are 4.22% and 128, respectively.