Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
A hierarchical design methodology for full-search block matching motion estimation
Multidimensional Systems and Signal Processing
Testable design techniques for variable block size motion estimator used in H.264/AVC
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
New pixel-decimation patterns for block matching in motion estimation
Image Communication
Binary Motion Estimation with Hybrid Distortion Measure
IEICE - Transactions on Information and Systems
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
A low-power and bandwidth-efficient motion estimation IP core design using binary search
IEEE Transactions on Circuits and Systems for Video Technology
«Motion estimation accelerator with user search strategy in an RVC context»
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
A content-motion-aware motion estimation for quality-stationary video coding
EURASIP Journal on Advances in Signal Processing
Testable design techniques for variable block size motion estimator used in H.264/AVC
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
A neighborhood elimination approach for block matching in motion estimation
Image Communication
Fuzzy quantization based bit transform for low bit-resolution motion estimation
Image Communication
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We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system and hardware implementation with parallel architectures. The key algorithm distinction is that only the high-frequency spectrum is used. Our experimental results show that it provides excellent performance at both low and high bit rates. Because of its binary-only representation, the proposed algorithm offers low computational complexity and low memory bandwidth consumption. For multimedia-embedded system design, we further investigated specific implementation techniques for several well-known hardware platforms including Intel x86 processors, single-instruction multiple-data processors, and systolic array circuit design. The systolic array architecture requires only single memory access for both the reference and current frames from the on-chip memory. Such an implementation provides an optimized solution with great throughput, while the quality is maintained. Finally, we show that our binarization methods are closely coupled to the accuracy of binary motion estimation algorithms. The binarization and coding efficiencies can be improved using various filters and binarization methods.