A binary block matching architecture with reduced power consumption and silicon area requirement
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
A novel low-power full-search block-matching motion-estimation design for H.263+
IEEE Transactions on Circuits and Systems for Video Technology
A novel all-binary motion estimation (ABME) with optimized hardware architectures
IEEE Transactions on Circuits and Systems for Video Technology
Global elimination algorithm and architecture design for fast block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Run-time adaptive energy-aware motion and disparity estimation in multiview video coding
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Adaptive power management of on-chip video memory for multiview video coding
Proceedings of the 49th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new architecture design for motion estimation using binary matching criterion is proposed to achieve low power and bus bandwidth efficiency. Low power and high bus bandwidth efficiency are the two key issues for portable video applications. To address such issues, we first study an efficient algorithm called all binary motion estimation (ABME), and analyze its architecture issues in operational flow and bus access. Then, we propose an architecture for ABME with four new features: 1) macroblock level pre-processing; 2) efficient binary pyramid search structure; 3) parallel processing of 8 × 8 and 16 × 16 block searches; 4) parallel processing of bi-directional search. Such architecture leads to a superior performance in bus access, speed, and power. Our experiments show that the power consumption is as low as 763µW for IPPPP CIF 30 frames/s and 896µW for IPBPB CIF 30 frames/s. The bus bandwidth savings are 54.3% for P-frame search and 67.1% for B-frame search.