Fine-grain leakage optimization in SRAM based FPGAs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations
IEEE Transactions on Computers
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chameleon: Application-Level Power Management
IEEE Transactions on Mobile Computing
Cache-based integer motion/disparity estimation for quad-HD H.264/AVC and HD multiview video coding
ICASSP '09 Proceedings of the 2009 IEEE International Conference on Acoustics, Speech and Signal Processing
A low-power and bandwidth-efficient motion estimation IP core design using binary search
IEEE Transactions on Circuits and Systems for Video Technology
Selective search area reuse algorithm for low external memory access motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A dynamic quality-adjustable H.264 video encoder for power-aware video applications
IEEE Transactions on Circuits and Systems for Video Technology
Multiview video coding based on rectified epipolar lines
ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Run-time adaptive energy-aware motion and disparity estimation in multiview video coding
Proceedings of the 48th Design Automation Conference
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
IEEE Transactions on Computers
Level C+ data reuse scheme for motion estimation with corresponding coding orders
IEEE Transactions on Circuits and Systems for Video Technology
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Efficient Prediction Structures for Multiview Video Coding
IEEE Transactions on Circuits and Systems for Video Technology
View-Adaptive Motion Estimation and Disparity Estimation for Low Complexity Multiview Video Coding
IEEE Transactions on Circuits and Systems for Video Technology
Adaptive power management of on-chip video memory for multiview video coding
Proceedings of the 49th Annual Design Automation Conference
A hierarchical control scheme for energy quota distribution in hybrid distributed video coding
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding
Proceedings of the Conference on Design, Automation and Test in Europe
Agent-based distributed power management for kilo-core processors
Proceedings of the International Conference on Computer-Aided Design
AMBER: adaptive energy management for on-chip hybrid video memories
Proceedings of the International Conference on Computer-Aided Design
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A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the leakage energy of the on-chip memory. The knowledge of motion and disparity estimation algorithm in conjunction with video properties are considered to predict the memory requirements of each Macroblock. A cost function is evaluated to determine an appropriate sleep mode for the idle memory sectors, while considering the wakeup overhead (latency and energy). The complete motion and disparity estimation architecture is implemented in a 65nm low power IBM technology. The experiments (for various test video sequences) demonstrate that our architecture provides up to 80% leakage energy reduction compared to state-of-the-art. Our scheme processes motion and disparity estimation of four HD1080p views encoding at 30fps with a power consumption of 57mW.