An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
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Active leakage power optimization for FPGAs
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Reducing leakage energy in FPGAs using region-constrained placement
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Proceedings of the 49th Annual Design Automation Conference
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FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.