A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Fine-grain leakage optimization in SRAM based FPGAs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power warp processor for power efficient high-performance embedded systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A Self-Adaptive Extensible Embedded Processor
SASO '07 Proceedings of the First International Conference on Self-Adaptive and Self-Organizing Systems
Run-time instruction set selection in a transmutable embedded processor
Proceedings of the 45th annual Design Automation Conference
An Overview of Low-Power Techniques for Field-Programmable Gate Arrays
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
Fine- and Coarse-Grain Reconfigurable Computing
Fine- and Coarse-Grain Reconfigurable Computing
Runtime Adaptive Extensible Embedded Processors -- A Survey
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Proceedings of the 2009 International Conference on Computer-Aided Design
KAHRISMA: a novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Field Programmability of Supply Voltages for FPGA Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the International Conference on Computer-Aided Design
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We propose a new way to save energy in adaptive processors. According to an execution context the custom instruction set of an adaptive processor is selectively 'muted' at run time and thus the energy efficiency is significantly increased. Implemented are multiple so-called 'muting modes' each leading to particular leakage energy savings. A key challenge of this work is to determine which of the muting modes are beneficial for which part of the custom instruction set in a specific execution context. We demonstrate the feasibility by means of an H.264 video encoder (although not limited to that) for various technology nodes. The complex and unpredictable processing behavior of an H.264 encoder represents thereby a real-world scenario. Our results show on average more than 30% energy savings compared to state-of-the-art. We claim that adaptive processors (and reconfigurable computing in general) would be far more energy efficient if FPGA vendors would provide a basic infrastructure that is necessary to exert our novel technique.