The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Combining low-leakage techniques for FPGA routing design
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Fine-grain leakage optimization in SRAM based FPGAs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Exploiting temporal idleness to reduce leakage power in programmable architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Energy-efficient FPGA interconnect design
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Leakage power reduction of embedded memories on FPGAs through location assignment
Proceedings of the 43rd annual Design Automation Conference
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Clock power reduction for virtex-5 FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA
IEICE - Transactions on Information and Systems
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed interconnect through device optimization for subthreshold FPGA
Microelectronics Journal
Performance analysis of FPGA interconnect fabric for ultra-low power applications
Proceedings of the 2011 International Conference on Communication, Computing & Security
Selective instruction set muting for energy-aware adaptive processors
Proceedings of the International Conference on Computer-Aided Design
A routing architecture for FPGAs with Dual-VT switch box and logic clusters
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Fully-functional FPGA prototype with fine-grain programmable body biasing
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Low power FPGA design using post-silicon device aging (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Off-path leakage power aware routing for SRAM-based FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Energy proportional computing in commercial FPGAs with adaptive voltage scaling
Proceedings of the 10th FPGAworld Conference
A FPGA prototype design emphasis on low power technique
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15%-30%.