Wiring requirement and three-dimensional integration technology for field programmable gate arrays

Authors:
Arifur Rahman;Shamik Das;Anantha P. Chandrakasan;Rafael Reif
Affiliations:
Polytechnic University, Brooklyn, NY;Microsystems Technology Laboratories, Michigan Institute of Technology, Cambridge, MA;Microsystems Technology Laboratories, Michigan Institute of Technology, Cambridge, MA;Microsystems Technology Laboratories, Michigan Institute of Technology, Cambridge, MA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Year:
2003

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Abstract

In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.