Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
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Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important when we deal with Digital System Processor (DSP) kernels, as there are demands for even higher clock frequencies and logic densities, which cannot be satisfied with existing design technologies. Three-dimensional (3D) integration is an emerging technology that promises to alleviate problems related to performance improvement, but up to now this new design approach has not been sufficiently explored. In this paper we propose a novel 3D FPGA architecture able to implement efficiently DSP applications. The proposed architecture is software-supported by a methodology targeting to explore DSP enhanced 3D FPGA devices. During our study we quantify a number of design parameters, such as the selected number of layers, the proper bonding approach, the process technology for each layer, etc. Comparison results prove the efficiency (in terms of performance and power consumption) of the new design paradigm, as compared to existing commercial devices with similar hardware resources.