DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Shrinking silicon technologies, increasing logic densities and clock frequencies on FPGA lead to rapid elevation in power density, which are translated to higher on-chip temperature. Recently, the FPGA industry (e.g. Xilinx, Altera) recognized the dominance of the heat problem as one of its key design issues, which should be tackled immediately. In this paper, considering a novel temperature-aware placement and routing algorithm, a systematic methodology to achieve a more "balanced" temperature distribution in the whole FPGA device, is introduced. Since the temperature is straightforwardrelated with the FPGA hardware resources switching activity, the main goal of the proposed methodology is to manipulate appropriately the switching activity appeared on different regions of the FPGA. Using the temperatureaware algorithm, we redistribute the switching activity over the FPGA resources, resulting into a rather "balanced" profile. Comparing with a conventionally-placed and routed FPGA (e.g. VPR), we proved that up to 33% temperature reduction in hotspots can be achieved with negligible side effects in circuit delay, energy/power consumption and silicon area. The proposed methodology is fully-supported by the software tool called EX - VPR