3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2003 international symposium on Physical design
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
3D Processing Technology and Its Impact on iA32 Microprocessors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal Trends in Emerging Technologies
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Thermal characterization and optimization in platform FPGAs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Thermally robust clocking schemes for 3D integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layer-Aware Design Partitioning for Vertical Interconnect Minimization
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Three-dimensional place and route for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Three-dimensional (3D) integration is an attractive and promising technology to keep Moore's Law alive, whereas the thermal issue also presents a critical challenge for 3D integrated circuits. Meanwhile, accurate thermal analysis is very time-consuming and thus can hardly be incorporated into most of placement algorithms generally performing numerous iterative refinement steps. As a consequence, in this paper, we first present a fine-grained grid-based thermal model for the 3D regular FPGA architecture and also highlight that lateral heat dissipation paths can no longer be assumed negligible. Then we propose two fast thermal-aware placement algorithms for 3D FPGAs, Standard Deviation (SD) and MineSweeper (MS), in which rapid thermal evaluation instead of slow detailed analysis is utilized. Moreover, both take the lateral heat dissipation into consideration and focus on distributing heat sources more evenly within a layer in a 3D FPGA to avoid creating hotspots. Experimental results show that SD and MS achieve 12.1%/7.6% reduction in maximum temperature and 82%/56% improvement in temperature deviation compared with a classical thermal-unaware placement method only at the cost of minor increase in wirelength and delay. Moreover, MS merely consumes 4% more runtime for producing thermal-aware placement solutions.