Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model

Authors:
Javid Jaffari;Mohab Anis
Affiliations:
University of Waterloo, Canada;University of Waterloo, Canada
Venue:
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Year:
2007

Citing 0
Cited 2

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only)

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

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Abstract

A thermal-aware placement is proposed for FPGAs to reduce the peak temperature and maximum on-chip gradient temperature. A new thermal cost is defined for the simulation annealing core of the placer based on the electrostatic charge model instead of extracting temperature profile in each simulation iteration. The thermal cost change rather than its actual value is derived to keep the runtime complexity of the cost evaluation algorithm linear with the number of used logic blocks. Results show an average of 73% and 51% reductions in the standard deviation and maximum gradient of temperature with less than 4% average wiring and delay penalty.