High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Wirelength-driven force-directed 3D FPGA placement
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A framework for architecture-level exploration of 3-D FPGA platforms
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Early stage power management for 3D FPGAs considering hierarchical routing resources
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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We present timing-driven partitioning and simulated-annealing (SA)-based placement algorithms together with a detailed routing tool for three-dimensional (3-D) field-programmable gate array (FPGA) integration. The circuit is first divided into layers with a limited number of interlayer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits, in terms of delay and wire length (WL), that 3-D technologies can offer for FPGA fabrics. Experimental results show, on average, a total decrease of 25% in WL and 35% in delay can be achieved over traditional two-dimensional chips, when ten layers are used in 3-D integration