Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Generic Universal Switch Blocks
IEEE Transactions on Computers
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
General Models and a Reduction Design Technique for FPGA Switch Box Designs
IEEE Transactions on Computers
Inversion of Symmetric Matrices in a New Block Packes Storage
NAA '00 Revised Papers from the Second International Conference on Numerical Analysis and Its Applications
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph Theory With Applications
Graph Theory With Applications
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
IEEE Transactions on Computers
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Configurable 3D-integrated focal-plane cellular sensor–processor array architecture
International Journal of Circuit Theory and Applications - Cellular Wave Computing Architecture
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation of a coupled-map-lattice-based cryptosystem
International Journal of Circuit Theory and Applications
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Three-dimensional place and route for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance Benefits of Monolithically Stacked 3-D FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for architecture-level exploration of 3-D FPGA platforms
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
A novel 3-D FPGA architecture targeting communication intensive applications
Journal of Systems Architecture: the EUROMICRO Journal
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Three-dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wire-length reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two-dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18-µm CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM-based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay-power product improvement and 43% area-delay product reduction. Copyright © 2010 John Wiley & Sons, Ltd.