Field-programmable gate arrays
Field-programmable gate arrays
An efficient incremental algorithm for solving systems of linear Diophantine equations
Information and Computation
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Directional bias and non-uniformity in FPGA global routing architectures
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Generic Universal Switch Blocks
IEEE Transactions on Computers
Detailed routing architectures for embedded programmable logic IP cores
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
A Three-Stage One-Sided Rearrangeable Polygonal Switching Network
IEEE Transactions on Computers
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Reduction design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
General Models and a Reduction Design Technique for FPGA Switch Box Designs
IEEE Transactions on Computers
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
On optimal hyperuniversal and rearrangeable switch box designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A New Approach for Rearrangeable Multicast Switching Networks
COCOA '09 Proceedings of the 3rd International Conference on Combinatorial Optimization and Applications
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
| Hi-index | 14.98 |
We consider the optimal design problem for arbitrary-shaped switch box, (r_1, \ldots, r_k){\hbox{-}}{\rm SB}, in which r_i terminals are located on side i for i = 1, \ldots, k and programmable switches are joining pairs of terminals from different sides. Previous investigations on switch box designs mainly focused on regular switch boxes in which all sides have the same number of terminals. By allowing different numbers of terminals on different sides, irregular switch boxes are more general and flexible for applications such as customized FPGAs and reconfigurable interconnection networks. The optimal switch box design problem is to design a switch box satisfying the given shape and routing capacity specifications with the minimum number of switches. We present a decomposition design method for a wide range of irregular switch boxes. The main idea of our method is to model a routing requirement as a nonnegative integer vector satisfying a system of linear equations and then derive a decomposition theory of routing requirements based on the theory of systems of linear Diophantine equations. The decomposition theory makes it possible to construct a large irregular switch box by combining small switch boxes of fixed sizes. Specifically, we can design a family of hyperuniversal (universal) (w {\bf{d}}+{\bf{c}}){\hbox{-}}{\rm SBs} with \Theta(w) switches, where {\bf{d}} and {\bf{c}} are constant vectors and w is a scalar. We illustrate the design method by designing a class of optimal hyperuniversal irregular 3-sided switch boxes and a class of optimal rectangular universal switch boxes. Experimental results on the rectangular universal switch boxes with the VPR router show that the optimal design of irregular switch boxes does pay off.