Field-programmable gate arrays
Field-programmable gate arrays
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the optimal four-way switch box routing structures of FPGA greedy routing architectures
Integration, the VLSI Journal
General models for optimum arbitrary-dimension FPGA switch box designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Graph Theory With Applications
Graph Theory With Applications
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA switch block layout and evaluation
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reduction design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analytical Framework for Switch Block Design
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Layout techniques for FPGA switch blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Augmented disjoint switch boxes for FPGAs
WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies
On improving FPGA routability applying multi-level switch boxes
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Crossbar based design schemes for switch boxes and programmable interconnection networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
IEEE Transactions on Computers
Routing architecture optimizations for high-density embedded programmable IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The exact channel density and compound design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Performance-driven dual-rail insertion for chip-level pre-fabricated design
Proceedings of the Conference on Design, Automation and Test in Europe
Reconfigurable Blocks Based on Balanced Ternary
Journal of Signal Processing Systems
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An FPGA switch box is said to be universal (hyper-universal) if it can detailed route all possible surrounding 2-pin (multi-pin) net topologies satisfying the global routing density constraints. A switch box is optimum if it is hyper-universal and the switches inside is minimum. It has been shown that if the net topology is restricted to 2-pin nets, then a 2-D (4-way) switch box can be built to be universal with only 6Wswitches, whereWis the global routing channel density. As the routing resource is relatively expensive in FPGA chips, study of the optimum switch box designs is clearly a topic with theoretical and commercial value of reducing silicon cost. A previous work has constructed a formal mathematical model of this optimum design problem for switch boxes with arbitrary dimensions, and gave a scheme to produce hyper-universal designs with less than 6.7W switches for 4-way FPGA switch boxes. In this paper, we will further investigate this most common 4-way switch box case, and will give new theoretical results followed by extensive experimental justification. The results seem to be quite attractive. We show that such an optimum switch box can be built with a very low number of additional switches beyond 6W for today's practical range of lowW's (e.g. just 6Wplus 1 or 2 additional switches forW's up to 7). Even for arbitrary largeW's, the bound can be shown to be under 6.34W. To make experimental comparison, we run today's published best FPGA router VPR on large benchmarks for the popular Disjoint structure and our proposed designs. The results are quite encouraging.