Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the optimal four-way switch box routing structures of FPGA greedy routing architectures
Integration, the VLSI Journal
Generic Universal Switch Blocks
IEEE Transactions on Computers
On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
Comment on Generic Universal Switch Blocks
IEEE Transactions on Computers
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
General models for optimum arbitrary-dimension FPGA switch box designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Graph Theory With Applications
Graph Theory With Applications
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Augmented disjoint switch boxes for FPGAs
WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies
Crossbar based design schemes for switch boxes and programmable interconnection networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
IEEE Transactions on Computers
The exact channel density and compound design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An edge ordering problem of regular hypergraphs
COCOON'06 Proceedings of the 12th annual international conference on Computing and Combinatorics
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A k-side switch block with W terminals per side is said to be a universal switch block ((k, W)-USB) if every set of the nets satisfying the routing constraint (i.e., the number of nets on each side is at most W) is simultaneously routable through the switch block. The (4, W)-USB was originated by designing better switch modules for 2-D FPGAs, such as Xilinx XC4000-type FPGAs, whereas the generic USBs can be applied in multidimensional or some nonconventional 2-D FPGA architectures. The problem we study in this article is to design (k, W)-USBs with the minimum number of switches for any given pair of (k, W). We provide graph models for routing requirements and switch blocks and develop a series of decomposition theorems for routing requirements with the help of a new graph model. The powerful decomposition theory leads to the automatic generation of routing requirements and a detailed routing algorithm, as well as the reduction design method of building large USBs by smaller ones. As a result, we derive a class of well-structured and highly scalable optimum (k, W)-USBs for k ≤ 6, or even Ws, and near-optimum (k, W)-USBs for k ≥ 7 and odd Ws. We also give routing experiments to justify the routing improvement upon the entire chip using the USBs. The results demonstrate the usefulness of USBs.