Field-programmable gate arrays
Field-programmable gate arrays
Switch box routing: a retrospective
Integration, the VLSI Journal
On a Class of Rearrangeable Networks
IEEE Transactions on Computers
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Universal switch blocks for three-dimensional FPGA design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
On the optimal four-way switch box routing structures of FPGA greedy routing architectures
Integration, the VLSI Journal
Generic Universal Switch Blocks
IEEE Transactions on Computers
A Three-Stage One-Sided Rearrangeable Polygonal Switching Network
IEEE Transactions on Computers
Reduction design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support
Integration, the VLSI Journal
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We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnected by a generic three-stage three-sided rearrangeable polygonal switching network (PSN). The main component of this PSN consists of a polygonal switch block interconnected by crossbars. In comparing our PSN with a three-stage three-sided clique-based (Xilinx 4000-like FPGAs) (Palczewski; 1992) switching network of the same size and with the same number of switches, we find that the three-stage three-sided clique-based switching network is not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters is determined to minimize the number of switches. Moreover, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that switches and speed performance are significantly improved. Based on experiment results, we can determine the parameters of PFPGA for the VLSI implementation.