Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Field-programmable gate arrays
Field-programmable gate arrays
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay
IEEE Transactions on Computers
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical interconnection structures for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving FPGA Routing Architectures Using Architecture and CAD Interactions
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Algorithms for an FPGA switch module routing problem with application to global routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinatorial routing analysis and design of universal switch blocks
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A Three-Stage One-Sided Rearrangeable Polygonal Switching Network
IEEE Transactions on Computers
Comment on Generic Universal Switch Blocks
IEEE Transactions on Computers
Reduction design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of FPGA/FPIC switch modules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
General Models and a Reduction Design Technique for FPGA Switch Box Designs
IEEE Transactions on Computers
On Optimum Designs of Universal Switch Blocks
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Layout techniques for FPGA switch blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crossbar based design schemes for switch boxes and programmable interconnection networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
IEEE Transactions on Computers
The exact channel density and compound design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy and switch area optimizations for FPGA global routing architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design automation for reconfigurable interconnection networks
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
| Hi-index | 14.99 |
A switch block $M$ with $W$ terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of $M$ is at most $W$) is simultaneously routable through $M$ [2]. In this paper, we present an algorithm to construct N-sided universal switch blocks with $W$ terminals on each side. Each of our universal switch blocks has ${{N}\choose{2}}W$ switches and switch-block flexibility$N-1$ (i.e., $F_S = N-1$). We prove that no switch block with less than ${{N}\choose{2}}W$ switches can be universal. We also compare our universal switch blocks with others of the topology associated with Xilinx XC4000-type FPGAs. To explore the area performance of the universal switch blocks, we develop a detailed router for hierarchical FPGAs (HFPGAs) with 5-sided switch blocks. Experimental results demonstrate that our universal switch blocks improve routability at the chip level. Based on extensive experiments, we also provide key insights into the interactions between switch-block architectures and routing.