Nonblocking Broadcast Switching Networks
IEEE Transactions on Computers
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generic Universal Switch Blocks
IEEE Transactions on Computers
A Three-Stage One-Sided Rearrangeable Polygonal Switching Network
IEEE Transactions on Computers
Superconcentrators, generalizers and generalized connectors with limited depth
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
The Mathematical Theory of Nonblocking Switching Networks (Series on Applied Mathematics)
The Mathematical Theory of Nonblocking Switching Networks (Series on Applied Mathematics)
Algorithms and Implementation for Interconnection Graph Problem
COCOA 2008 Proceedings of the 2nd international conference on Combinatorial Optimization and Applications
A New Approach for Rearrangeable Multicast Switching Networks
COCOA '09 Proceedings of the 3rd International Conference on Combinatorial Optimization and Applications
On optimal hyperuniversal and rearrangeable switch box designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set embedding for deterministic BIST using a reconfigurable interconnection network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
R-NoC: an efficient packet-switched reconfigurable networks-on-chip
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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A Reconfigurable Interconnection Network (RIN) is a custom designed on-chip switching network yielding routing solutions for a pre-given set of applications. Like FPGA routing networks, the RIN is used to make reconfigurable interconnections among functional blocks. Unlike FPGAs, the network topology of a RIN is irregular as it is designed for a given set of routing requirements and optimized for area, power and delay minimizations. In this paper, we propose an automatic design scheme for RINs, including routing specification formulation, graph modelings, network topology designs, routing algorithms, and MUX-based network circuit implementation. A CAD tool is developed based on the design scheme, which takes a set of routing requirements as input and produces the corresponding RIN network topology and network circuit in HDL format. We present the area costs of various RINs generated by the CAD tool with Altera’s Quartus II, and illustrate the RIN design scheme with a reconfigurable multi-stream video system prototype.