Field-programmable gate arrays
Field-programmable gate arrays
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design automation for reconfigurable interconnection networks
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Networks-on-Chip (NoC) architectures have been proposed to replace the classical bus and point-to-point global interconnections for the next generation of multiple-core systems-on-a-chips. However, the one-to-one (unicast) based NoC communication paradigm is not efficient for one-to-many (multicast) communication requests, and the address based packet routing method lacks the capability to arrange routing globally for overall communication performance. To address these problems, we here propose a Reconfigurable NoC (R-NoC) architecture. The novelty of the R-NoC is that a structured virtual routing path can be established through the reconfiguration of routers so that packets are delivered fast along the pre-configured routing path. Load balance for overall communication performance can be achieved through the global arrangement of routing paths. In addition, custom network topology is proposed for specific set of applications to reduce the costs on area and power. Software simulations show that the structured data path approach has a significant performance improvement on multicast comparing with the traditional multiple unicast approach.