A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
An approach to incremental design of distributed embedded systems
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Hard real-time scheduling for low-energy using stochastic data and DVS processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Self-Similar Network Traffic and Performance Evaluation
Self-Similar Network Traffic and Performance Evaluation
Worst-case traffic for oblivious routing functions
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Wormhole Switching with Adaptive Routing in a Two-Dimensional Torus
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Energy Aware Scheduling for Distributed Real-Time Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Energy characterization of a tiled architecture processor with on-chip networks
Proceedings of the 2003 international symposium on Low power electronics and design
Energy optimization techniques in cluster interconnects
Proceedings of the 2003 international symposium on Low power electronics and design
Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Networks on chip
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Design of Resonant Global Clock Distributions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
On-chip networks: A scalable, communication-centric embedded system design paradigm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Iterative schedule optimization for voltage scalable distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism
Proceedings of the 31st annual international symposium on Computer architecture
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High-level power analysis for on-chip networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 42nd annual Design Automation Conference
Frequency-based code placement for embedded multiprocessors
Proceedings of the 42nd annual Design Automation Conference
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Compiler-directed voltage scaling on communication links for reducing power consumption
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
GALS networks on chip: a new solution for asynchronous delay-insensitive links
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Supporting task migration in multi-processor systems-on-chip: a feasibility study
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Towards Open Network-on-Chip Benchmarks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Using the inter- and intra-switch regularity in NoC switch testing
Proceedings of the conference on Design, automation and test in Europe
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method
Proceedings of the conference on Design, automation and test in Europe
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Congestion-controlled best-effort communication for networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
Temperature aware task scheduling in MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Introducing the SuperGT network-on-chip: SuperGT QoS: more than just GT
Proceedings of the 44th annual Design Automation Conference
Layered switching for networks on chip
Proceedings of the 44th annual Design Automation Conference
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Run-time adaptive on-chip communication scheme
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Equalized interconnects for on-chip networks: modeling and optimization framework
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Journal of Systems Architecture: the EUROMICRO Journal
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Computers
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
Proceedings of the 2nd International Workshop on Network on Chip Architectures
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scheduling framework for real-time dependable NoC-based systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Efficient lookahead routing and header compression for multicasting in networks-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Convex-based DOR routing for virtualization of NoC
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Floorplanning and topology generation for application-specific network-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
Journal of Systems Architecture: the EUROMICRO Journal
Network-on-Chip interconnect for pairing-based cryptographic IP cores
Journal of Systems Architecture: the EUROMICRO Journal
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture
Proceedings of the Third International Workshop on Network on Chip Architectures
An analytical approach for network-on-chip performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A networks-on-chip emulation/verification framework
International Journal of High Performance Systems Architecture
System design of full HD MVC decoding on mesh-based multicore NoCs
Microprocessors & Microsystems
Hermes-a - an asynchronous NoC router with distributed routing
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Inferring packet dependencies to improve trace based simulation of on-chip networks
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework
Proceedings of the 24th symposium on Integrated circuits and systems design
Real-time communication analysis for networks with two-stage arbitration
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ROBUST: a new self-healing fault-tolerant NoC router
Proceedings of the 4th International Workshop on Network on Chip Architectures
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
Making-a-stop: A new bufferless routing algorithm for on-chip network
Journal of Parallel and Distributed Computing
Static task mapping for tiled chip multiprocessors with multiple voltage islands
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
A generic and non-intrusive profiling methodology for systemc multi-core platform simulation models
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Model-based analysis tools for component synthesis
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
Sustainable multi-core architecture with on-chip wireless links
Proceedings of the great lakes symposium on VLSI
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Intelligent on/off dynamic link management for on-chip networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
R-NoC: an efficient packet-switched reconfigurable networks-on-chip
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A novel NoC-based design for fault-tolerance of last-level caches in CMPs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A high-efficiency low-cost heterogeneous 3D network-on-chip design
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Reliable noc mapping based on scatter search
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip
Journal of Parallel and Distributed Computing
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Network-on-chip traffic modeling for data flow applications
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping
Microprocessors & Microsystems
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
ACM Transactions on Embedded Computing Systems (TECS)
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
Journal of Computer and System Sciences
Research on half-mesh topology based on binary model and HTF-XY routing algorithm
International Journal of Computer Applications in Technology
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
Simultaneous multithreading support in embedded distributed memory MPSoCs
Proceedings of the 50th Annual Design Automation Conference
A multi-agent framework for thermal aware task migration in many-core systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UNISM: unified scheduling and mapping for general networks on chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An MILP-based aging-aware routing algorithm for NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
An energy-aware online task mapping algorithm in NoC-based system
The Journal of Supercomputing
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
On heterogeneous network-on-chip design based on constraint programming
Proceedings of the Sixth International Workshop on Network on Chip Architectures
An analytical model for on-chip interconnects in multimedia embedded systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 2D Mesh NoC using LBDRe
International Journal of Embedded and Real-Time Communication Systems
Power consumption of 3D networks-on-chips: Modeling and optimization
Microprocessors & Microsystems
Energy and buffer aware application mapping for networks-on-chip with self similar traffic
Journal of Systems Architecture: the EUROMICRO Journal
Microprocessors & Microsystems
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs
Microprocessors & Microsystems
NoC-based fault-tolerant cache design in chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure
Computers and Electrical Engineering
Systolic traffic modelling in network on chip
International Journal of Wireless and Mobile Computing
Hi-index | 0.03 |
To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.