Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Rate-optimal schedule for multi-rate DSP computations
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Multiprocessor mapping of process networks: a JPEG decoding case study
Proceedings of the 15th international symposium on System Synthesis
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
Journal of VLSI Signal Processing Systems
A Large-Area Integrated Multiprocessor System for Video Applications
IEEE Design & Test
A Pipeline-Based Approach for Scheduling Video Processing Algorithms on NOW
IEEE Transactions on Parallel and Distributed Systems
Guaranteeing the quality of services in networks on chip
Networks on chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Proceedings of the 43rd annual Design Automation Conference
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Online resource management in a multiprocessor with a network-on-chip
Proceedings of the 2007 ACM symposium on Applied computing
Modelling run-time arbitration by latency-rate servers in dataflow graphs
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal
Parametric throughput analysis of synchronous data flow graphs
Proceedings of the conference on Design, automation and test in Europe
Distributed Performance Control in Organic Embedded Systems
ATC '08 Proceedings of the 5th international conference on Autonomic and Trusted Computing
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modular performance analysis of cyclic dataflow graphs
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
Abstraction-based performance verification of NoCs
Proceedings of the 48th Design Automation Conference
Static dataflow with access patterns: semantics and analysis
Proceedings of the 49th Annual Design Automation Conference
DART--a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
Journal of Signal Processing Systems
Modeling static-order schedules in synchronous dataflow graphs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Flexible filters in stream programs
ACM Transactions on Embedded Computing Systems (TECS)
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We consider a dynamic application running on a multiprocessor network-on-chip as a set of independent jobs, each job possibly running on multiple processors. To provide guaranteed quality and performance, the scheduling of jobs, jobs themselves and the hardware must be amenable to timing analysis. For a certain class of applications and multiprocessor architectures, we propose exact timing models that effectively co-model both the computation and communication of a job. The models are based on interprocessor communication (IPC) graphs [4]. Our main contribution is a precise model of network-on-chip communication, including buffer models. We use a JPEG-decoder job as an example to demonstrate that our models can be used in practice to derive upper bounds on the job execution time and to reason about optimal buffer sizes.