Holistic schedulability analysis for distributed hard real-time systems
Microprocessing and Microprogramming - Parallel processing in embedded real-time systems
Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Approximate algorithms for time separation of events
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Scheduling Parallel Computations
Journal of the ACM (JACM)
A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
Performance Guarantees in Communication Networks
Performance Guarantees in Communication Networks
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the 40th annual Design Automation Conference
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Workload Characterization Model for Tasks with Variable Execution Demand
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
System architecture evaluation using modular performance analysis: a case study
International Journal on Software Tools for Technology Transfer (STTT)
Analysis of manufacturing blocking systems with network calculus
Performance Evaluation
Proceedings of the conference on Design, automation and test in Europe
Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Cyclic dependencies in modular performance analysis
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Lightweight Modeling of Complex State Dependencies in Stream Processing Systems
RTAS '09 Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Performance analysis of latency-insensitive systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case performance analysis of synchronous dataflow scenarios
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NC-maude: a rewriting tool to play with network calculus
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
ACM Transactions on Embedded Computing Systems (TECS)
Dataflow analysis for multiprocessor systems with non-starvation-free schedulers
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
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Applications for parallel and distributed embedded systems are often specified as dataflow graphs with dependency cycles. Examples of corresponding models of computation are marked graphs or synchronous dataflow (SDF) graphs. Performance analysis is often used in the exploration of different implementation alternatives or in order to provide guarantees on the timing behavior. This paper describes a new approach to the modular performance analysis of cyclic dataflow graphs such as SDF graphs as existing component-based analysis methods are not able to faithfully deal with cycles in the event flow. The new method results in tight bounds on essential quantities like buffer sizes, end-to-end delays and throughput. Because of the generality of the approach, one can analyze not only systems that can be modeled as marked graphs but also implementations that contain buffers with finite sizes, that produce system-wide back-pressure caused by blocking write semantics. The embedding of the novel approach into a modular performance analysis method allows the analysis of distributed implementations that use resource sharing mechanisms such as fixed-priority scheduling and time division multiple access (TDMA). The paper presents the new models and methods as well as experimental results.