VLSI array processors
Introduction to algorithms
Supercompilers for parallel and vector computers
Supercompilers for parallel and vector computers
A data locality optimizing algorithm
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Multirate systems and filter banks
Multirate systems and filter banks
Looped schedules for dataflow descriptions of multirate signal processing algorithms
Formal Methods in System Design
Optimizing Supercompilers for Supercomputers
Optimizing Supercompilers for Supercomputers
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Mulitdimensional Streams Rooted in Dataflow
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Partitioning VLSI Floorplans by Staircase Channels for Global Routing
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
3D exploration of software schedules for DSP algorithms
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Multidimensional Exploration of Software Implementationsfor DSP Algorithms
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
A code generation framework for Java component-based designs
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Phased scheduling of stream programs
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
Proceedings of the 31st annual international symposium on Computer architecture
Design methodology for SoC arthitectures based on reusable virtual cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 4th ACM international conference on Embedded software
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Retargeting Sequential Image-Processing Programs for Data Parallel Execution
IEEE Transactions on Software Engineering
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
Cache aware optimization of stream programs
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Conversion of reference C code to dataflow model: H.264 encoder case study
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
VCore-based design methodology
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Synthesis for SoC architecture using VCores
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Real-Time Camera Tracking for Mobile Devices: The VisiTrack System
Real-Time Systems
Particle-based methodology for representing mobile ad-hoc networks
InterSense '06 Proceedings of the first international conference on Integrated internet ad hoc and sensor networks
Proceedings of the 43rd annual Design Automation Conference
A model-based extensible framework for efficient application design using FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing code size in VLIW instruction scheduling
Journal of Embedded Computing - Low-power Embedded Systems
Hierarchical coarse-grained stream compilation for software defined radio
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Minimizing Place Capacities of Weighted Event Graphs for Enforcing Liveness
Discrete Event Dynamic Systems
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Exact and approximate task assignment algorithms for pipelined software synthesis
Proceedings of the conference on Design, automation and test in Europe
Modular performance analysis of cyclic dataflow graphs
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Energy-driven distribution of signal processing applications across wireless sensor networks
ACM Transactions on Sensor Networks (TOSN)
Minimizing communication in rate-optimal software pipelining for stream programs
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Journal of Systems Architecture: the EUROMICRO Journal
Iterative probabilistic performance prediction for multi-application multiprocessor systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Automated bottleneck-driven design-space exploration of media processing systems
Proceedings of the Conference on Design, Automation and Test in Europe
Model-based synthesis and optimization of static multi-rate image processing algorithms
Proceedings of the Conference on Design, Automation and Test in Europe
Constrained global scheduling of streaming applications on MPSoCs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Synchroscalar: initial lessons in power-aware design of a tile-based embedded architecture
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
StreamX10: a stream programming framework on X10
Proceedings of the 2012 ACM SIGPLAN X10 Workshop
Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral Transparency
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A SWP specification for sequential image processing algorithms
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio
Journal of Signal Processing Systems
A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memory
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
StreamTMC: Stream compilation for tiled multi-core architectures
Journal of Parallel and Distributed Computing
Modeling static-order schedules in synchronous dataflow graphs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.00 |
The implementation of software for embedded digital signalprocessing (DSP) applications is an extremely complex process. Thecomplexity arises from escalating functionality in the applications;intense time-to-market pressures; and stringent cost, power and speedconstraints. To help cope with such complexity, DSP system designershave increasingly been employing high-level, graphical designenvironments in which system specification is based on hierarchicaldataflow graphs. Consequently, a significant industry has emergedfor the development of data-flow-based DSP design environments.Leading products in this industry include SPW from Cadence, COSSAPfrom Synopsys, ADS from Hewlett Packard, and DSP Station from MentorGraphics. This paper reviews a set of algorithms for compilingdataflow programs for embedded DSP applications into efficientimplementations on programmable digital signal processors. Thealgorithms focus primarily on the minimization of code size, and theminimization of the memory required for the buffers that implementthe communication channels in the input dataflow graph. These arecritical problems because programmable digital signal processors havevery limited amounts of on-chip memory, and the speed, power, andcost penalties for using off-chip memory are often prohibitively highfor embedded applications. Furthermore, memory demands ofapplications are increasing at a significantly higher rate than therate of increase in on-chip memory capacity offered by improvedintegrated circuit technology.