MIPS RISC architectures
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Hardware/software partitioning of embedded system in OCAPI-xl
Proceedings of the ninth international symposium on Hardware/software codesign
Source-level execution time estimation of C programs
Proceedings of the ninth international symposium on Hardware/software codesign
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
VCore-based design methodology
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VCore-based platform for SoC design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design methodology for SoC arthitectures based on reusable virtual cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
VCore-based platform for SoC design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A PN-based approach to the high-level synthesis of digital systems
Integration, the VLSI Journal
A PN-based approach to the high-level synthesis of digital systems
Integration, the VLSI Journal
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In this paper, we propose a novel architecture synthesis method for SoC using VCores. VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architecture's performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.