Design methodology for SoC arthitectures based on reusable virtual cores

Authors:
Michiaki Muraoka;Hiroaki Nishi;Rafael K. Morizawa;Hideaki Yokota;Hideyuki Hamada
Affiliations:
Semiconductor Technology Academic Research Center (STARC), Kohoku-ku, Yokohama, Japan;Semiconductor Technology Academic Research Center (STARC), Kohoku-ku, Yokohama, Japan;Semiconductor Technology Academic Research Center (STARC), Kohoku-ku, Yokohama, Japan;Semiconductor Technology Academic Research Center (STARC), Kohoku-ku, Yokohama, Japan;Semiconductor Technology Academic Research Center (STARC), Kohoku-ku, Yokohama, Japan
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

Citing 12
Cited 0

MIPS RISC architectures

MIPS RISC architectures
Hardware-software co-design of embedded systems: the POLIS approach

Hardware-software co-design of embedded systems: the POLIS approach
Hardware/software partitioning of embedded system in OCAPI-xl

Proceedings of the ninth international symposium on Hardware/software codesign
Synthesis of Embedded Software from Synchronous Dataflow Specifications

Journal of VLSI Signal Processing Systems
Hardware-Software Cosynthesis for Digital Systems

IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers

IEEE Design & Test
A Decade of Hardware/Software Codesign

Computer
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
VCore-based design methodology

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Synthesis for SoC architecture using VCores

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VCore-based platform for SoC design

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Integrating communication protocol selection with hardware/software codesign

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The design reuse methodology, which has been developed at the VCDS Project, is a SoC design methodology to reduce the SoC design time using high level design intellectual properties named as Virtual Cores (VCores). In this paper, we propose the VCore based design methodology to synthesize the SoC architecture from the system level specification. This synthesis methodology generates an initial architecture that consists of a CPU, buses, I/Os peripherals, and RTOS (Real Time Operating System), and makes tradeoffs between hardware and software on assigned software VCores and hardware Vcores models to the architecture. The results of an architecture level design experiment using the proposed methodology shows that the partial automation of the communication refinement process, allied with design reuse, accelerates the architecture synthesis, thus reducing the design time required to design an architecture.