A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits

Authors:
Toshinori Hosokawa;Hiroshi Date;Michiaki Muraoka
Affiliations:
-;-;-
Venue:
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Year:
2002

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Abstract

This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.