Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Fractional Rate Dataflow Model for Efficient Code Synthesis
Journal of VLSI Signal Processing Systems
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
Throughput Analysis of Synchronous Data Flow Graphs
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Efficient computation of buffer capacities for cyclo-static dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs
IEEE Transactions on Computers
Practical and Accurate Throughput Analysis with the Cyclo Static Dataflow Model
MASCOTS '07 Proceedings of the 2007 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Throughput Constraint for Synchronous Data Flow Graphs
CPAIOR '09 Proceedings of the 6th International Conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems
Monotonicity and run-time scheduling
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Automated bottleneck-driven design-space exploration of media processing systems
Proceedings of the Conference on Design, Automation and Test in Europe
Worst-case performance analysis of synchronous dataflow scenarios
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Model-Based Schedule Representation for Heterogeneous Mapping of Dataflow Graphs
IPDPSW '11 Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Energy-aware task mapping and scheduling for reliable embedded computing systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
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Synchronous dataflow graphs (SDFGs) are used extensively to model streaming applications. An SDFG can be extended with scheduling decisions, allowing SDFG analysis to obtain properties like throughput or buffer sizes for the scheduled graphs. Analysis times depend strongly on the size of the SDFG. SDFGs can be statically scheduled using static-order schedules. The only generally applicable technique to model a static-order schedule in an SDFG is to convert it to a homogeneous SDFG (HSDFG). This conversion may lead to an exponential increase in the size of the graph and to sub-optimal analysis results (e.g., for buffer sizes in multi-processors). We present a technique to model periodic static-order schedules directly in an SDFG. Experiments show that our technique produces more compact graphs compared to the technique that relies on a conversion to an HSDFG. This results in reduced analysis times for performance properties and tighter resource requirements.