Introduction to Linear Optimization
Introduction to Linear Optimization
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
Journal of VLSI Signal Processing Systems
A comparison of synchronous and cycle-static dataflow
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 43rd annual Design Automation Conference
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Signal Processing
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Parametric throughput analysis of synchronous data flow graphs
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Cache aware mapping of streaming applications on a multiprocessor system-on-chip
Proceedings of the conference on Design, automation and test in Europe
Monotonicity and run-time scheduling
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Reduction techniques for synchronous dataflow graphs
Proceedings of the 46th Annual Design Automation Conference
Look into details: the benefits of fine-grain streaming buffer analysis
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Synchronous dataflow scenarios
ACM Transactions on Embedded Computing Systems (TECS)
Buffer capacity computation for throughput-constrained modal task graphs
ACM Transactions on Embedded Computing Systems (TECS)
Analysis of SystemC actor networks for efficient synthesis
ACM Transactions on Embedded Computing Systems (TECS)
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
Correct and non-defensive glue design using abstract models
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Static dataflow with access patterns: semantics and analysis
Proceedings of the 49th Annual Design Automation Conference
Cache-conscious scheduling of streaming applications
Proceedings of the twenty-fourth annual ACM symposium on Parallelism in algorithms and architectures
Compositional temporal analysis model for incremental hard real-time system design
Proceedings of the tenth ACM international conference on Embedded software
Analytical approaches for performance evaluation of networks-on-chip
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Sequential specification of time-aware stream processing applications
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Cyclo-static DataFlow phases scheduling optimization for buffer sizes minimization
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
Dataflow analysis for multiprocessor systems with non-starvation-free schedulers
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
Buffer minimization in earliest-deadline first scheduling of dataflow graphs
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
Modeling static-order schedules in synchronous dataflow graphs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Maximum-throughput mapping of SDFGs on multi-core SoC platforms
Journal of Parallel and Distributed Computing
| Hi-index | 0.01 |
A key step in the design of cyclo-static real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure, which means that tasks wait for space in output buffers. Consequently buffer capacities affect the throughput. This requires the derivation of buffer capacities that both result in a satisfaction of the throughput constraint, and also satisfy the constraints on the maximum buffer capacities. Existing exact solutions suffer from the computational complexity that is associated with the required conversion from a cyclo-static dataflow graph to a single-rate dataflow graph. In this paper we present an algorithm, with polynomial computational complexity, that does not require this conversion and that obtains close to minimal buffer capacities. The algorithm is applied to an MP3 play-back application that is mapped on our multi-processor system. For this application, we see that a cyclo-static dataflow model can reduce the buffer capacities by 50% compared to a multi-rate dataflow model.