On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Digital receiver design using VHDL generation from data flow graphs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Computer
A Compositional Rule for Hardware Design Refinement
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
Proceedings of the 12th international symposium on System synthesis
Undecidable problems of decentralized observation and control on regular languages
Information Processing Letters
Software synthesis from the dataflow interchange format
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Synthesis of Synchronous Interfaces
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Efficient computation of buffer capacities for cyclo-static dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
Distributed reactive systems are hard to synthesize
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs
IEEE Transactions on Computers
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
Synthesis from Component Libraries
FOSSACS '09 Proceedings of the 12th International Conference on Foundations of Software Science and Computational Structures: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
The earlier the better: a theory of timed actor interfaces
Proceedings of the 14th international conference on Hybrid systems: computation and control
Synthesizing Hardware from Dataflow Programs
Journal of Signal Processing Systems
The hierarchical timing pair model for multirate DSP applications
IEEE Transactions on Signal Processing
Static dataflow with access patterns: semantics and analysis
Proceedings of the 49th Annual Design Automation Conference
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Current hardware design practice often relies on integration of components, some of which may be IP or legacy blocks. While integration eases design by allowing modularization and component reuse, it is still done in a mostly ad hoc manner. Designers work with descriptions of components that are either informal or incomplete (e.g., documents in English, structural but non-behavioral specifications in IP-XACT) or too low-level (e.g., HDL code), and have little to no automatic support for stitching the components together. Providing such support is the glue design problem. This paper addresses this problem using a model-based approach. The key idea is to use high-level models, such as dataflow graphs, that enable efficient automated analysis. The analysis can be used to derive performance properties of the system (e.g., component compatibility, throughput, etc.), optimize resource usage (e.g., buffer sizes), and even synthesize low-level code (e.g., control logic). However, these models are only abstractions of the real system, and often omit critical information. As a result, the analysis outcomes may be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). The paper examines these situations and proposes a correct and non-defensive design methodology that employs the right models to explore accurate performance and resource trade-offs.