Digital receiver design using VHDL generation from data flow graphs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Memory efficient software synthesis with mixed coding style from dataflow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Generating mixing hardware/software systems from SDL specifications
Proceedings of the ninth international symposium on Hardware/software codesign
Synthesis of hardware models in C with pointers and complex data structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Efficient code synthesis from extended dataflow graphs for multimedia applications
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Mapping multirate dataflow to complex RT level hardware models
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
On the Importance, Problems and Solutions of Pointer Synthesis
Proceedings of the 15th symposium on Integrated circuits and systems design
Hardware-software codesign with GRAPE
RSP '95 Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP'95)
Code Generation of Data Dominated DSP Applications for FPGA Targets
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
Proceedings of the 12th international symposium on System synthesis
Fractional Rate Dataflow Model for Efficient Code Synthesis
Journal of VLSI Signal Processing Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multidimensional DSP Core Synthesis for FPGA
Journal of VLSI Signal Processing Systems
Multidimensional synchronous dataflow
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correct and non-defensive glue design using abstract models
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Static dataflow with access patterns: semantics and analysis
Proceedings of the 49th Annual Design Automation Conference
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This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.