Multidimensional DSP Core Synthesis for FPGA

  • Authors:

  • J. Mcallister;R. Woods;R. Walke;D. Reilly

  • Affiliations:

  • Programmable Systems Laboratory, Institute of Electronics, Communication and Information Technology (ECIT), Queen's University Belfast, Belfast, UK BT3 9DT;Programmable Systems Laboratory, Institute of Electronics, Communication and Information Technology (ECIT), Queen's University Belfast, Belfast, UK BT3 9DT;Aff1 Aff2;Programmable Systems Laboratory, Institute of Electronics, Communication and Information Technology (ECIT), Queen's University Belfast, Belfast, UK BT3 9DT

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2006

Quantified Score

Hi-index 0.00

Visualization

Abstract

Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense.