High Speed FPGA-Based Implementations of Delayed-LMS Filters

Authors:
Y. Yi;R. Woods;L. K. Ting;C. F. N. Cowan
Affiliations:
Programmable System Laboratory, School of Electrical and Electronic Engineering, Queen's University Belfast, Northern Ireland;Programmable System Laboratory, School of Electrical and Electronic Engineering, Queen's University Belfast, Northern Ireland;Intel Microelectronics (M) SDN, Malaysia;Programmable System Laboratory, School of Electrical and Electronic Engineering, Queen's University Belfast, Northern Ireland
Venue:
Journal of VLSI Signal Processing Systems
Year:
2005

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Abstract

A variation of the least means squares (LMS) algorithm, called the delayed LMS (DLMS) algorithm is ideally suited for highly pipelined, adaptive digital filter implementations. In this paper, we present an efficient method to determine the delays in the DLMS filter. Furthermore, in order to achieve fully pipelined circuit architectures for FPGA implementation, we transfer these delays using retiming. The method has been used to derive a series of retimed delayed LMS (RDLMS) architectures, which allow a 66.7% reduction in delays and 5 times faster convergence time thereby giving superior performance in terms of throughput rate when compared to previous work. Three circuit architectures and three hardware shared versions are presented which have been implemented using the Virtex-II FPGA technology resulting in a throughput rate of 182 Msample/s.