VLSI array processors
Computer-based tools for regular array design
Systolic array processors
On the use of most significant digit first arithmetic in the design of high performance DSP chips
Proceedings of the international workshop on Algorithms and parallel VLSI architectures II
VLSI Design Methodologies for Digital Signal Processing Architectures
VLSI Design Methodologies for Digital Signal Processing Architectures
Anatomy of a Silicon Compiler
Efficient exploration of affine space-time transformations for optimal systolic array synthesis
Efficient exploration of affine space-time transformations for optimal systolic array synthesis
PHIDEO: a silicon compiler for high speed algorithms
EURO-DAC '91 Proceedings of the conference on European design automation
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Linear QR Architecture for a Single Chip Adaptive Beamformer
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
DG2VHDL: A Tool to Facilitate the High Level Synthesisof Parallel Processing Array Architectures
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Design of a parameterizable Silicon intellectual property core for QR-based RLS filtering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Speed FPGA-Based Implementations of Delayed-LMS Filters
Journal of VLSI Signal Processing Systems
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In this paper, we present the IRIS architectural synthesis system forhigh-performance digital signal processing. This tool allowsnon-specialists to automatically derive VLSI circuit architecturesfrom high-level, algorithmic representations, and provides a quickroute to silicon implementation. By incorporating a novel synthesismethodology, called the Modular Design Procedure, within the IRISsystem, parameterised models of complex and innovative DSP hardwarecan be derived and automatically assembled to create new DSPsystems. The nature of this synthesis methodology is such thatdesigners can explore a large range of architectural alternatives,whilst considering all the architectural implications of usingspecific hardware to realise the circuit. The applicability of IRISis demonstrated using the design examples of a second order InfiniteImpulse Response filter and a one-dimensional Discrete CosineTransform circuit.