Design of a parameterizable Silicon intellectual property core for QR-based RLS filtering

Authors:
Gaye Lightbody;Roger Woods;Richard Walke
Affiliations:
Intellectual Property Company, Amphion Semiconductor Ltd., Belfast, BT9 5BS, Northern Ireland and School of Electrical and Electronic Engineering, Queen's University of Belfast, Belgast BT9 5AH, N ...;School of Electrical and Electronic Engineering, Queen's University Belfast, Belfast BT9 5AH, Northern Ireland;Real-Time Embedded Systems Group, QinetiQ Ltd., Malvern WR14 3PS, U.K.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2003

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Abstract

The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hard-ware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.