Linear QR Architecture for a Single Chip Adaptive Beamformer

Authors:
G. Lightbody;R. Walke;R. Woods;J. McCanny
Affiliations:
DSiP^TM Laboratories, Queen's University of Belfast,Belfast, N. Ireland;DERA, St. Andrew's Road, Malvern, England;Hardware Systems Group, Queen's University of Belfast, Belfast, N. Ireland;DSiP^TM Laboratories, Queen's University of Belfast, Belfast,
Venue:
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Year:
2000

Citing 6
Cited 2

Adaptive filter theory

Adaptive filter theory
VLSI array processors

VLSI array processors
Adaptive system identification and signal processing algorithms

Adaptive system identification and signal processing algorithms
Architectural Synthesis of Digital Signal ProcessingAlgorithms Using “IRIS”

Journal of VLSI Signal Processing Systems - Special issue on the 1995 VLSI signal processing workshop
Digital Beamforming in Wireless Communications

Digital Beamforming in Wireless Communications
Hierarchical VHDL Libraries for DSP ASIC Design6

ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1

A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection

Journal of VLSI Signal Processing Systems
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA

APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the design of a novel single chip adaptivebeamformer capable of performing50 Gflops, (Giga-floating-point operations/second). The core processoris a QR array implemented on afully efficient linear systolic architecture, derived using a mappingthat allows individualprocessors for boundary and internal cell operations. In addition, thepaper highlights a number ofrapid design techniques that have been used to realise this system.These include an architecturesynthesis tool for quickly developing the circuit architecture and theutilisation of a library ofparameterisable silicon intellectual property (IP) cores, to rapidlydevelop detailed silicon designs.