Adaptive filter theory (2nd ed.)
Adaptive filter theory (2nd ed.)
Matrix computations (3rd ed.)
Linear QR Architecture for a Single Chip Adaptive Beamformer
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
Iterative QR Detection for BLAST
Wireless Personal Communications: An International Journal
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
The next generation challenge for software defined radio
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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MIMO has been proposed as an extension to 3G and Wireless LANs. As an implementation scheme of MIMO systems, V-BLAST is suitable for the applications with very high data rates. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to its low computational complexity and numerical stability. In this paper, the fixed-point implementation of the square root algorithm is analyzed, and a low complexity VLSI architecture is proposed. The proposed architecture is scalable for various configurations, and implemented for a 4 脳 4 QPSK V-BLAST system in a 0.35 $\mu$ m CMOS technology. The chip core covers 9 $mm^2$ and 190 K gates. The detection throughput of the chip depends on the received symbol packet length. When the packet length is larger than or equal to 100 bytes, it can achieve a maximal detection throughput of 128 $\sim$ 160 Mb/s at a maximal clock frequency of 80 MHz. The core power consumption, measured at 2.7 V and room temperature, is about 608 mW for 160 Mb/s data rate at 80 MHz, and 81 mW for 20 Mb/s at 10 MHz. The proposed architecture is shown to meet the requirements for emerging MIMO applications, such as 3G HSDPA and IEEE 802.11n.