DG2VHDL: A Tool to Facilitate the High Level Synthesisof Parallel Processing Array Architectures

Authors:
Andrew Stone;Elias S. Manolakos
Affiliations:
Electrical and Computer Engineering Department, Northeastern University, Boston, MA, USA;Electrical and Computer Engineering Department, Northeastern University, Boston, MA, USA
Venue:
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Year:
2000

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Abstract

We present DG2VHDL, a design tool which can automaticallytranslate abstract algorithmic descriptions, known as DependenceGraphs, to synthesizable VHDL models and testbenches representativeof distributed memory and control processor arrays, known asSignal Flow Graphs. This translation facilitates the rapidexploration of the large space of available parallel architecturesfor a given problem and frees the designer from having to code andtest separately, using a Hardware Description Language, everycandidate architecture under consideration. It is shown that thequality and scalability of the automatically generated VHDLmodels is near optimal, in the sense that the time required tosynthesize them as well as the area of the resulting hardware growsat the lowest possible rate with the problem size. This makespossible the high level synthesis of processor arrays for large sizereal world problems, such as the computation of the Discrete WaveletTransform and the estimation of Higher Order Statistics, that arepresented as case studies.