High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fitting formal methods into the design cycle
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combined control flow dominated and data flow dominated high-level synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Domain-specific high-level modeling and synthesis for ATM switch design using VHDL
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The maximal VHDL subset with a cycle-level abstraction
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
System design using an integrated specification and performance modeling methodology
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '98 Proceedings of the 35th annual Design Automation Conference
DG2VHDL: A Tool to Facilitate the High Level Synthesisof Parallel Processing Array Architectures
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
A methodology for verifying memory access protocols in behavioral synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Observable Time Windows: Verifying High-Level Synthesis Results
IEEE Design & Test
Observable Time Windows: Verifying the Results of High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Embedded Architecture Co-Synthesis and System Integration
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Synthesis of low-power selectively-clocked systems from high-level specification
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A memory aware behavioral synthesis tool for real-time VLSI circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Memory accesses management during high level synthesis
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Rapid industrial prototyping and SoC design of 3G/4G wireless systems using an HLS methodology
EURASIP Journal on Embedded Systems
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