Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
IEEE Transactions on Signal Processing
A programming environment for the design of complex high speed ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient error detection, localization, and correction for FPGA-based debugging
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Functional and Performance Modeling of Concurrency in VCC
Concurrency and Hardware Design, Advances in Petri Nets
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A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modern design from the link level to the gate level. The methodology uses a C++-based untimed dataflow system description, which is gradually refined to an optimized, bit-true and clock cycle true C++-description. Through this refinement, a bridge from link level design semantics to architectural VHDL semantics is made within one and the same environment.