Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Locally clocked pipelines and dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementing asynchronous circuits using a conventional EDA tool-flow
Proceedings of the 39th annual Design Automation Conference
Logic Synthesis and Verification
A Methodology for the Formal Analysis of Asynchronous Micropipelines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Programming Approach to the Design of Asynchronous Logic Blocks
Concurrency and Hardware Design, Advances in Petri Nets
Automating the design of an asynchronous DLX microprocessor
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A hybrid asynchronous system design environment
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
AMULET3: A 100 MIPS Asynchronous Embedded Processor
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
The design of a low power asynchronous multiplier
Proceedings of the 2004 international symposium on Low power electronics and design
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A lattice-based framework for the classification and design of asynchronous pipelines
Proceedings of the 42nd annual Design Automation Conference
A Coarse-Grain Phased Logic CPU
IEEE Transactions on Computers
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Integrated Computer-Aided Engineering
Global critical path: a tool for system-level timing analysis
Proceedings of the 44th annual Design Automation Conference
Self-resetting latches for asynchronous micro-pipelines
Proceedings of the 44th annual Design Automation Conference
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Operation chaining asynchronous pipelined circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Serialized asynchronous links for NoC
Proceedings of the conference on Design, automation and test in Europe
Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part IV: ICCS 2007
Slack analysis in the system design loop
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The design of an asynchronous blocksorter
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
A VHDL-based design methodology for asynchronous circuits
WSEAS Transactions on Circuits and Systems
The design of a simple asynchronous processor
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
The design of sharing resources for asynchronous systems
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
Modeling and synthesis of asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An evaluation for the design of asynchronous systems
WSEAS Transactions on Circuits and Systems
An optimization for the design of a simple asynchronous processor
WSEAS Transactions on Computers
Design of an asynchronous switch based on butterfly fat-tree for network-on-chip applications
PCM'05 Proceedings of the 6th Pacific-Rim conference on Advances in Multimedia Information Processing - Volume Part II
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Properties as processes: their specification and verification
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
QDI latches characteristics and asynchronous linear-pipeline performance analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Bounded model checking for parametric timed automata
Transactions on Petri Nets and Other Models of Concurrency V
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are level sensitive, so two- to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques.