Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication

Authors:
Sunan Tugsinavisut;Youpyo Hong;Daewook Kim;Kyeounsoo Kim;Peter A. Beerel
Affiliations:
Electrical Engineering Department, University of Southern California, Los Angeles, CA;Electrical Engineering Department, Dongguk University, Seoul 100-715, Korea;Electrical Engineering Department, Dongguk University, Seoul 100-715, Korea;Examination Bureau of Electrical and Electronics Engineering of Korean Intellectual Property Office, Daejeon 302-701, Korea;Electrical Engineering Department, University of Southern California, Los Angeles, CA and Fulcrum Microsystems, Calabasas Hills, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

This paper demonstrates the design of efficient asynchronous bundled-data pipelines for the matrix-vector multiplication core of discrete cosine transforms (DCTs). The architecture is optimized for both zero and small-valued data, typical in DCT applications, yielding both high average performance and low average power. The proposed bundled-data pipelines include novel data-dependent delay lines with integrated control circuitry to efficiently implement speculative completion sensing. The control circuits are based on a novel control-circuit template that simplifies the design of such nonlinear pipelines. Extensive post-layout back-end timing analysis was performed to gain confidence in the timing margins as well as to quantify performance and energy. Comparison with a synchronous counterpart suggests that our best asynchronous design yields 30% higher average throughput with negligible energy overhead.