On the models for designing VLSI asynchronous digital systems
Integration, the VLSI Journal
Communications of the ACM
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Low-latency asynchronous FIFO buffers
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Designing an asynchronous pipeline token ring interface
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A lattice-based framework for the classification and design of asynchronous pipelines
Proceedings of the 42nd annual Design Automation Conference
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Formal methods for scheduling of latency-insensitive designs
EURASIP Journal on Embedded Systems
APCR: an adaptive physical channel regulator for on-chip interconnects
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Design and test of self-checking asynchronous control circuit
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
| Hi-index | 0.00 |
We propose a new methodology to design asynchronous circuits that is divided in two stages: abstract synthesis and logic synthesis. The first stage is carried out by refining an abstract model, based on logic predicates describing the correct input-output behavior of the circuit, into a labeled Petri net and then into a formalization of timing diagrams (the Signal Transition Graph). This refinement involves hierarchical decomposition of the initial implementation until its size can be handled by automated logic synthesis tools, as well as replacing symbolic events occurring on the input-output ports of the labeled Petri net with up and down transitions occurring on the input-output wires of a circuit implementation.