Communication and concurrency
Communications of the ACM
Selected papers of the Second Workshop on Concurrency and compositionality
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Representing and modeling digital circuits
Representing and modeling digital circuits
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesizing Petri nets from state-based models
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of asynchronous circuits using time Petri net unfolding
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Methodology and tools for state encoding in asynchronous circuit synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
High-Level Modeling and Design of Asynchronous Interface Logic
IEEE Design & Test
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
On the Correctness of the Sproull Counterflow Pipeline Processor
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Cellular arrays for asynchronous control
MICRO 7 Conference record of the 7th annual workshop on Microprogramming
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
The Design Problem SCPP-A
Synthesising elementary net systems with inhibitor arcs from step transition systems
Fundamenta Informaticae - Application of concurrency to system design
Concurrent Implementation of Asynchronous Transition Systems
Proceedings of the 20th International Conference on Application and Theory of Petri Nets
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
IEEE Transactions on Computers
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Synthesising Elementary Net Systems with Inhibitor Arcs from Step Transition Systems
Fundamenta Informaticae - Application of Concurrency to System Design
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This paper approaches the problem of synthesising an asynchronouscontrol circuit for a stage of the Sproull Counterflow pipeline processor(CFPP) as an exercise in exploiting formal techniques available for Petrinets. We first synthesise a Petri net model of the CFPP stage control fromits original “five-state-five-event” description due toCharles Molnar. Secondly, we implement that model in asynchronouscircuits, using two-phase and four-phase components. The latter stageinvolves synthesising circuits with arbitration elements from behaviouraldescriptions with internal conflicts. This exercise appears to be quiteinstructive in the sense that it helps to estimate the scope and power offormal methods and today‘s automatic tools in assisting the process ofasynchronous design.