Selected papers of the Second Workshop on Concurrency and compositionality
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Methodology and tools for state encoding in asynchronous circuit synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings
Formal Methods in System Design
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Efficient encoding schemes for symbolic analysis of petri nets
Proceedings of the conference on Design, automation and test in Europe
Synthesising elementary net systems with inhibitor arcs from step transition systems
Fundamenta Informaticae - Application of concurrency to system design
On Concurrent Realization of Reactive Systems and Their Morphisms
Unifying Petri Nets, Advances in Petri Nets
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Discovery, Verification and Conformance of Workflows with Cancellation
ICGT '08 Proceedings of the 4th international conference on Graph Transformations
Merging Event-Driven Process Chains
OTM '08 Proceedings of the OTM 2008 Confederated International Conferences, CoopIS, DOA, GADA, IS, and ODBASE 2008. Part I on On the Move to Meaningful Internet Systems:
Assessing State Spaces Using Petri-Net Synthesis and Attribute-Based Visualization
Transactions on Petri Nets and Other Models of Concurrency I
Process Mining: Overview and Outlook of Petri Net Discovery Algorithms
Transactions on Petri Nets and Other Models of Concurrency II
Synthesising Elementary Net Systems with Inhibitor Arcs from Step Transition Systems
Fundamenta Informaticae - Application of Concurrency to System Design
The Synthesis Problem for Elementary Net Systems with Inhibitor Arcs
Fundamenta Informaticae
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This paper presents a method to synthesize labeled Petri nets from state-based models. Although state-based models (such as Finite State Machines) are a powerful formalism to describe the behavior of sequential systems, they cannot explicitly express the notions of concurrency, causality and conflict. Petri nets can naturally capture these notions. The proposed method in based on deriving an Elementary Transition System (ETS) from a specification model. Previous work has shown that for any ETS there exists a Petri net with minimum transition count (one transition for each label) with a reachability graph isomorphic to the original ETS. This paper presents the first known approach to obtain an ETS from a non-elementary TS and derive a place-irredundant Petri net. Furthermore, by imposing constraints on the synthesis method, different classes of Petri nets can be derived from the same reachability graph (pure, free choice, unique choice). This method has been implemented and efficiently applied in different frameworks: Petri net composition, synthesis of Petri nets from asynchronous circuits, and resynthesis of Petri nets.