Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Synthesizing Petri nets from state-based models
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Model Checking Using Net Unfoldings
TAPSOFT '93 Proceedings of the International Joint Conference CAAP/FASE on Theory and Practice of Software Development
A survey of equivalence notions for net based systems
Advances in Petri Nets 1992, The DEMON Project
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
OR Causality: Modelling and Hardware Implementation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
Petri Net Analysis Using Boolean Manipulation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
Checking signal transition graph implementability by symbolic BDD traversal
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Scheduling analysis of FMS: an unfolding timed Petri nets approach
Mathematics and Computers in Simulation - Special issue: Computational engineering in systems applications (CESA 2003)
Hardware and Petri nets: application to asynchronous circuit design
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
Structuring acyclic process models
BPM'10 Proceedings of the 8th international conference on Business process management
Generalised computation of behavioural profiles based on petri-net unfoldings
WS-FM'10 Proceedings of the 7th international conference on Web services and formal methods
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This paper suggests a way for Petri Net analysis by checkingthe ordering relations between places and transitions. The method isbased on unfolding the original net into an equivalent acyclicdescription. We improved on the previously known cutoff criterionfor truncating unfoldings [13]. No restrictions are imposed on theclass of general PNs. The new criterion significantly reduces thesize of an unfolding obtained by a PN. The properties of PNs foranalysis can be various: boundedness, safety, persistency etc. Apractical example of the suggested approach is given in an applicationto asynchronous design. Circuit behavior is specified by aninterpreted Petri net, called a Signal Transition Graph (STG) which isthen analyzed for implementability by an asynchronous hazard-freecircuit. The implementability conditions are formulated in such a waythat they can be checked by analysis of ordering relations betweensignal transitions rather than by traversal of states. This allows usto avoid the state explosion problem for highly parallelspecifications. The experimental results show that for highlyparallel STGs checking their implementability by an unfolding is oneto two orders of magnitude less time-consuming than checking it bysymbolic BDD traversal of the corresponding State Graph.